Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - vhdl jpeg

Search list

[VHDL-FPGA-Verilog] DCT_IDCT

Description: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Platform: | Size: 29696 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] huffman

Description: 用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 10240 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] rle

Description: 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 4096 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] zigzag

Description: 用于FPGA的Z变化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-脫脙脫脷FPGA渭脛Z 卤 盲 禄炉 脣茫 篓 渭脛HDL 卤 脿脗毛 拢 卢 掳 眉脌 篓 VHDL 录 掳 Verilog
Platform: | Size: 7168 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] zigzag_decode

Description: 用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 3072 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] JPEGvhdl

Description: JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.
Platform: | Size: 260096 | Author: 姚大雷 | Hits:

[Picture Viewer] JPEGactFPGA

Description: 利用FPGA实现JPEG算法的研究与实现，研究生的论文，很有参考价值-JPEG algorithm using FPGA realization of Research and Implementation of, post-graduate thesis, a good reference
Platform: | Size: 2592768 | Author: 刘小春 | Hits:

[Picture Viewer] fpga-jpeg

Description: fpga based jpge 压缩算法， 性能不错，-fpga based jpge compression algorithm, performance good,
Platform: | Size: 104448 | Author: sloanyang | Hits:

[Picture Viewer] jpeg_rgb

Description: 这是JPEG图像压缩的RGB转换的源代码，其中还包括了它的仿真测试代码，希望能帮助到大家。-This is the JPEG image compression of RGB conversion source code, including its simulation test code, hoping to help you.
Platform: | Size: 3072 | Author: mary | Hits:

[Compress-Decompress algrithms] buffer_img

Description: buffer image coefficents for jpeg compression
Platform: | Size: 1024 | Author: sandeep | Hits:

[Software Engineering] nowy

Description: enkoder jpeg - very good-enkoder jpeg- very good
Platform: | Size: 2359296 | Author: student | Hits:

[VHDL-FPGA-Verilog] oc_mkjpeg

Description: Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
Platform: | Size: 3267584 | Author: Andy | Hits:

[Industry research] etd-0901103-165524

Description: jpeg 2000 modules with definate improved design ideas on the hardware platorm. especiallyy EBCOT and MQ coder.
Platform: | Size: 1027072 | Author: junk | Hits:

[VHDL-FPGA-Verilog] jpeg.tar

Description: vhdl source for jpeg beginner
Platform: | Size: 1869824 | Author: ksh | Hits:

[VHDL-FPGA-Verilog] fpga_jpeg

Description: 图像jpeg压缩算法,用verilog HDL在FPGA上的实现 -Jpeg image compression algorithm, using verilog HDL Implementation in FPGA
Platform: | Size: 103424 | Author: 沧海一笑 | Hits:

[Picture Viewer] jpeg_decoder

Description: JPEG hardware decode RTL code
Platform: | Size: 296960 | Author: Jon Lee | Hits:

[VHDL-FPGA-Verilog] FPGA_image

Description: fpga实现图像处理，JPEG标准下图象压缩，VHDL语言编程。-fpga implementation image processing, JPEG image compression under the standard, VHDL language programming.
Platform: | Size: 295936 | Author: xiangchuiyi | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[Special Effects] jpeg_encoder.tar

Description: jpeg解码器，给出了详细的结构介绍，同时也对端口和使用配置做了详细说明-jpeg decoder, gives a detailed description of the structure, but also using the configuration of the ports and a detailed description
Platform: | Size: 2232320 | Author: nickye | Hits:
« 1 23 4 5 »

CodeBus www.codebus.net